Semiconductors,
& RF
Silicon, RF and mixed-signal engineering for Australia's fabless and deep-tech firms.
Chip design, RF SOC, mixed-signal and analog engineering talent for Australia's growing fabless semiconductor and wireless silicon ecosystem. We work with the firms designing the silicon at the heart of Wi-Fi HaLow, IoT, low-power wireless, and specialist RF applications.
What we do here
This is one of the deepest specialist markets we work in. The candidate pool is small enough that a senior search effectively becomes a named-target campaign — we know who the realistic candidates are before we begin, and the work is to engage them on terms that respect how senior the role is.
Most of our engagements here are retained executive search or research-led specialist recruitment. Contingent does not work in a pool this small.
What “great” looks like at intake
A clear technical brief is essential — generic chip-design briefs do not produce useful shortlists in this market. We need to know the specific domain (RF front-end vs digital baseband vs analog), the node (28nm, 14nm, 7nm), the methodology (RTL/UVM vs schematic/SPICE), and the design phase the firm is hiring for. We will pressure-test all of these on the first call.
Recent engagements in this sector
Confidential mandates with Sydney-based fabless firms designing wireless silicon for the IoT and consumer-device markets. Full details under NDA on a confidential call.
Capabilities we cover
- ▸ RF and mixed-signal IC design
- ▸ Digital design and verification (RTL, UVM, SystemVerilog)
- ▸ Analog and mixed-signal circuit design
- ▸ PHY, MAC and wireless protocol engineering
- ▸ Physical design, place-and-route, DFT
- ▸ Silicon validation and post-silicon characterisation
Typical roles & bands
- Senior RF / Mixed-Signal IC Designer$170k–$230k base
- Senior Digital Design Engineer (RTL)$160k–$220k base
- Senior Verification Engineer (UVM)$160k–$220k base
- Senior Analog Design Engineer$170k–$230k base
- Silicon Validation Engineer$140k–$190k base
- Design Manager / IC Lead$220k–$320k total
- Source. The founder's placement records across 15 years of recruitment practice, continuing into AEY, plus ongoing market benchmarking.
- Composition. Base salary unless otherwise specified. Total-comp roles include equity / bonus / day-rate where stated.
- Variance. Actual offers move with stage, location, technical specialism, clearance status and the candidate's alternative options. The bands above are 25th–75th percentile, not floor and ceiling.
- Currency. All amounts in AUD.
Market notes
Australia's fabless semiconductor scene is small, well-funded and quietly world-class. Firms designing wireless SOCs, RFICs, and specialist silicon out of Sydney compete directly with US and Taiwanese teams for talent — and increasingly win. The candidate universe in the country is genuinely tiny; most senior chip engineers know each other, have worked together once, and choose where to go based on the technical interest of the work first and compensation second.
Highly concentrated in Sydney with smaller pools in Melbourne and Adelaide. Many engineers have prior experience at international firms (Apple, Broadcom, Qualcomm) and have repatriated.
Anonymised, never shared. Maintained as a live working map, not a database.
Let's talk about semiconductors & rf.
A 30-minute call is enough for us to know whether we can add value - and whether you should be talking to us, or to someone else.